• VLSI Logic Design
• Senior / Lead Level Engineers
• Experience: 3 - 10 years
• Must have:
  • Experience in RTL / Verification / Synthesis / DFT / Gatesim
  • Knowledge of Verilog, System Verilog and C/C++
  • Led full-fledged reusable, silicon proven IP development effort
  • Worked on USB 3, PCI Express, SATA, EMAC, WI-FI, DDR, MIPI protocols
  • Capacity to assimilate protocols thoroughly and capability to take them to compliance
  • Familiarity with AMBA bus structure and must have developed some of the bus components
    
    

Engineers who lead development of verification environment for any IP using system verilog and have a flair for venturing into other front-end areas are welcome.

To apply for jobs,send your resume to careers@soctronics.com