SoCtronics has over the years of extensive project execution, developed customized in-house tools to leverage the best in class EDA solutions and extend them to offer significant differentiation in power performance metrics be they high performance processor implementations, networking SoCs or power optimized ultra mobile hand-held SoCs.
RTL to GDSII execution leverages proven in-house tools & flows like Advanced Chipbuilder Tool (ACT), SmartPower (SMP) and Rapid Characterization Engine (RaCE) in addition to leveraging the best in class 3rd party EDA solutions from Cadence, Synopsys, Mentor Graphics and Magma.
A state-of-the-art design flow engine that seamlessly integrates all aspects of RTL to GDSII execution seamlessly leveraging state of the art 3rd party EDA tools in various phases of the design including database management, compute and license utilization & design flow management.
A state-of-the-art low power to take your design beyond what standard EDA tools provide. Seamlessly integrated into ACT (or can be run standalone) it enables complex designs with power islands, integrated (coarse and fine grain) power gating, multi-voltage designs, automated power grid generation and low power verification.
An in-house characterization flow for combination cells which enables performance optimization by circuit hardening as needed and rapid characterization of cells to be integrated into the design libraries.
Multiple flow solutions are available which leverage standard reference flows from EDA vendors along with the above in-house enhancements.
Leverage "G" and "HP" type technology variants for superior performance for CPU, GPU, Networking requirements. Tailored design flows with in-house utilities for timing performance optimization. Leverages Multi-Vt device option for quick timing fixes.
Leverage "LP", "HPL" type technology variants for leakage reduction. In-house experts can provide power performance analysis to decide the right technology node and transistor mix options. In-house SmartPower flow enabled for micro-architecture to device level optimizations enabling power gating, multi-Vcc domains, multi-Vt and CD Bias options.
Design flows can be tailored to cater to a wide range of design requirements. SoCtronics experts are available to help guide the right design flow solution for every requirement.